Huawei details Ascend 950/960/970 roadmap and Atlas 950/960 “SuperPoDs” — a direct volley at NVIDIA’s data-center lead

At HUAWEI CONNECT 2025, Huawei publicly laid out a multi-year Ascend AI chip roadmap (950/960/970) and unveiled massive Atlas 950 and Atlas 960 “SuperPoD” systems scaling to 8,192 and 15,488 NPUs. It’s a statement of domestic compute ambition—and a direct challenge to NVIDIA’s cluster economics.

What Huawei actually announced

• Chips: Ascend 950 (two variants) targeted for 2026; Ascend 960 in 2027; Ascend 970 in 2028—on an annual cadence with step-function compute increases. Huawei also talked up HiF8/HiF4 data formats and expanded vector throughput.
• Systems: Atlas 950 SuperPoD scales to 8,192 NPUs; Atlas 960 SuperPoD stretches to 15,488 NPUs. Messaging emphasizes a new UnifiedBus interconnect and mesh topology designed for linear scaling and “single-computer” behavior at rack scale.
• Memory: Huawei signaled progress on in-house high-bandwidth memory—closing a former choke point for China’s supply chain.

Why this matters

Even if NVIDIA keeps absolute performance leadership with GB200 NVL72 and successor platforms, Huawei’s pitch is about controllable supply and whole-stack integration. In a market where Chinese regulators have urged firms to avoid certain NVIDIA SKUs, a domestic accelerator with a credible software stack is leverage. We unpacked the policy context in our analysis of Beijing’s tech posture.

The engineering questions that decide real-world impact

1. Interconnect math: To make 8k–15k NPU pods useful, you need NVLink-class latency and bandwidth with predictable congestion control. Huawei’s UnifiedBus claims a recursive direct-connect mesh. Scrutinize bisection bandwidth, failure domains, and how it handles collective ops (AllReduce, MoE gating, KV cache sharding).
2. Memory locality & formats: Proprietary HiF8/HiF4 could be pragmatic, but toolchains must map PyTorch/TensorRT-like kernels without loss. Compiler maturity and kernel autotuning will make or break advertised efficiency.
3. Software friction: CUDA’s gravity well is real. The credibility test is end-to-end training runs (MLPerf, public pretrain logs) and reproducible inference throughput on open models. A robust CANN/Ascend toolchain with stable kernels is non-negotiable.

Procurement lens: who buys this and why?

Chinese internet platforms, finance, and state-linked research are obvious early adopters. The calculus is: acceptable perf/$, reduced sanctions risk, and multi-year visibility on parts. Expect dual-track deployments—Ascend clusters for domestic work, NVIDIA clusters abroad—glued by cross-compile and serving gateways.

Reality checks

• Delivery risk: Chip cadence plus interconnect innovation is a tall order; memory packaging and optical interposer yields can bottleneck.
• Benchmarks: Huawei and local media have touted cases where its systems “outperform” NVIDIA on select metrics; treat these as claims until third-party MLPerf or public training logs land.
• Policy volatility: Export-control tweaks that touch optics, reticle limits, or HBM supply could force design detours.

For readers modelling capacity, pair this piece with our N2 node explainer (power/thermals compound at scale) and our VRAM guide for workstation inference budgets.